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ASPLOS
1998
ACM
13 years 12 months ago
Fast Out-Of-Order Processor Simulation Using Memoization
Our new out-of-order processor simulator, FastSim, uses two innovations to speed up simulation 8–15 times (vs. Wisconsin SimpleScalar) with no loss in simulation accuracy. First...
Eric Schnarr, James R. Larus
ICS
2004
Tsinghua U.
14 years 1 months ago
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures
The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute...
Rajeev Balasubramonian
ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
14 years 1 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
IJCAI
2003
13 years 9 months ago
Learning Value Predictors for the Speculative Execution of Information Gathering Plans
Speculative execution of information gathering plans can dramatically reduce the effect of source I/O latencies on overall performance. However, the utility of speculation is clos...
Greg Barish, Craig A. Knoblock
IJCAI
2003
13 years 9 months ago
Combining Classification and Transduction for Value Prediction in Speculative Plan Execution
Speculative execution of information gathering plans can dramatically reduce the effect of source I/O latencies on overall performance. However, the utility of speculation is clos...
Greg Barish, Craig A. Knoblock