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ISCA
2000
IEEE
90views Hardware» more  ISCA 2000»
14 years 11 hour ago
A scalable approach to thread-level speculation
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
ISLPED
2003
ACM
87views Hardware» more  ISLPED 2003»
14 years 26 days ago
On load latency in low-power caches
Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional late...
Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Ir...
VLDB
2002
ACM
141views Database» more  VLDB 2002»
13 years 7 months ago
A Multi-version Cache Replacement and Prefetching Policy for Hybrid Data Delivery Environments
This paper introduces MICP, a novel multiversion integrated cache replacement and prefetching algorithm designed for efficient cache and transaction management in hybrid data deli...
André Seifert, Marc H. Scholl
EUROPAR
2005
Springer
14 years 1 months ago
Improving Instruction Delivery with a Block-Aware ISA
Instruction delivery is a critical component for wide-issue processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and ba...
Ahmad Zmily, Earl Killian, Christos Kozyrakis
DAMON
2008
Springer
13 years 9 months ago
Avoiding version redundancy for high performance reads in temporal databases
A major performance bottleneck for database systems is the memory hierarchy. The performance of the memory hierarchy is directly related to how the content of disk pages maps to t...
Khaled Jouini, Geneviève Jomier