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ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
14 years 13 hour ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
FCCM
2005
IEEE
84views VLSI» more  FCCM 2005»
14 years 1 months ago
Prototyping Architectural Support for Program Rollback Using FPGAs
This paper presents a processor and memory-hierarchy prototype based on FPGAs that provides hardware support for program rollback. We use this prototype to demonstrate how compile...
Radu Teodorescu, Josep Torrellas
IPPS
2007
IEEE
14 years 1 months ago
A Minimal Access Cost-Based Multimedia Object Replacement Algorithm
Multimedia object caching, by which the same multimedia object can be adapted to diverse mobile appliances through the technique of transcoding, is an important technology for imp...
Keqiu Li, Takashi Nanya, Wenyu Qu
AI
2008
Springer
13 years 7 months ago
Speculative plan execution for information gathering
The execution performance of an information gathering plan can suffer significantly due to remote I/O latencies. A streaming dataflow model of execution addresses the problem to s...
Greg Barish, Craig A. Knoblock
CODES
2008
IEEE
14 years 2 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...