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ISQED
2005
IEEE
78views Hardware» more  ISQED 2005»
14 years 14 days ago
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction
Abstract— To achieve small delay and low crosstalk for multiple signal nets with capacitive and inductive coupling, we propose in this paper a novel interconnect structure, stagg...
Hao Yu, Lei He
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
12 years 10 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
DATE
2003
IEEE
120views Hardware» more  DATE 2003»
14 years 5 days ago
Crosstalk Reduction in Area Routing
Interconnect delay dominates system delay in modern circuits, and with reduced feature sizes, coupling capacitance and signal crosstalk have become significant issues. By spacing...
Ryon M. Smey, Bill Swartz, Patrick H. Madden
ICCD
2004
IEEE
120views Hardware» more  ICCD 2004»
14 years 3 months ago
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs
This paper describes XTalkDelay, an industrial-strength methodology and tool for measuring the impact of crosstalk on delays of paths in a design. The main cornerstone of XTalkDel...
Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwin...
24
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ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
14 years 14 days ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra