1186 search results - page 4 / 238 » State machine models of timing and circuit design |
EGPGV
2011
Springer
12 years 11 months ago
2011
Springer
We present a state of the art read-only distributed shared memory (DSM) ray tracer capable of fully utilizing modern cluster hardware to render massive out-of-core polygonal model...
DFT
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
ICCD
1995
IEEE
13 years 11 months ago
1995
IEEE
We describe thedesign of a high performance asynchronous SCSI Small Computer Systems Interface controller data path and the associated control circuits. The data path is an asyn...
DATE
2000
IEEE
14 years 1 days ago
2000
IEEE
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
In current research, the minimum cycle times of finite state machines are estimated by computing the delays of the combinational logic in the finite state machines. Even though th...