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» Static Energy Reduction Techniques for Microprocessor Caches
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RTSS
2003
IEEE
14 years 26 days ago
Data Caches in Multitasking Hard Real-Time Systems
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...
Xavier Vera, Björn Lisper, Jingling Xue
MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
14 years 26 days ago
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
Se-Hyun Yang, Babak Falsafi
ESTIMEDIA
2009
Springer
13 years 5 months ago
Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories
Abstract--Memory accesses are a major cause of energy consumption for embedded systems and the stack is a frequent target for data accesses. This paper presents a fully software te...
Lovic Gauthier, Tohru Ishihara
ISLPED
2005
ACM
98views Hardware» more  ISLPED 2005»
14 years 1 months ago
Synonymous address compaction for energy reduction in data TLB
Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, m...
Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, M...
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
14 years 1 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt