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» Static Scheduling for Synchronous Data Flow Graphs
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ICCAD
1994
IEEE
104views Hardware» more  ICCAD 1994»
13 years 10 months ago
Module selection and data format conversion for cost-optimal DSP synthesis
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
DAC
1996
ACM
13 years 11 months ago
Lower Bounds on Test Resources for Scheduled Data Flow Graphs
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breue...
DSN
2006
IEEE
14 years 23 days ago
Static Analysis to Enforce Safe Value Flow in Embedded Control Systems
Embedded control systems consist of multiple components with different criticality levels interacting with each other. For example, in a passenger jet, the navigation system inter...
Sumant Kowshik, Grigore Rosu, Lui Sha
DATE
2002
IEEE
123views Hardware» more  DATE 2002»
13 years 11 months ago
False Path Elimination in Quasi-Static Scheduling
We have developed a technique to compute a Quasi Static Schedule of a concurrent specification for the software partition of an embedded system. Previous work did not take into a...
G. Arrigoni, L. Duchini, Claudio Passerone, Lucian...
NSDI
2010
13 years 8 months ago
Hedera: Dynamic Flow Scheduling for Data Center Networks
Today's data centers offer tremendous aggregate bandwidth to clusters of tens of thousands of machines. However, because of limited port densities in even the highest-end swi...
Mohammad Al-Fares, Sivasankar Radhakrishnan, Barat...