— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
Lieven Vandenberghe, Stephen P. Boyd, Abbas A. El ...
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
This paper presents an implementation of feedback control strategy on distributed static scheduling. The static schedule is created taking into account the average execution times...
The Hardware (HW)/Software (SW) partitioning/scheduling relies on two subtasks : the cost function and the real time (RT) analysis. Besides these two subtasks, the proposed generi...
This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Convention...
Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao ...