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» Static timing analysis for modeling QoS in networks-on-chip
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DAC
2004
ACM
14 years 8 months ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
DATE
2008
IEEE
204views Hardware» more  DATE 2008»
14 years 2 months ago
Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis
Shrinking feature sizes and process variations are of increasing concern in modern technology. It is urgent that we develop statistical interconnect timing models which are harmon...
Jun-Kuei Zeng, Chung-Ping Chen
TCAD
2008
98views more  TCAD 2008»
13 years 7 months ago
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
Khaled R. Heloue, Farid N. Najm
ICCAD
2001
IEEE
104views Hardware» more  ICCAD 2001»
14 years 4 months ago
A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells
We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simu...
Clayton B. McDonald, Randal E. Bryant
WWW
2011
ACM
13 years 2 months ago
A word at a time: computing word relatedness using temporal semantic analysis
Computing the degree of semantic relatedness of words is a key functionality of many language applications such as search, clustering, and disambiguation. Previous approaches to c...
Kira Radinsky, Eugene Agichtein, Evgeniy Gabrilovi...