306 search results - page 11 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
SLIP
2006
ACM
14 years 1 months ago
2006
ACM
Crosstalk aggressor alignment induces significant interconnect delay variation and needs to be taken into account in a statistical timer. In this paper, we approximate crosstalk ...
VLSID
1997
IEEE
13 years 11 months ago
1997
IEEE
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
ICLP
2009
Springer
14 years 8 months ago
2009
Springer
PRISM is a probabilistic extension of Prolog. It is a high level language for probabilistic modeling capable of learning statistical parameters from observed data. After reviewing ...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
PATMOS
2004
Springer
14 years 21 days ago
2004
Springer
The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...