306 search results - page 13 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
GLVLSI
2000
IEEE
13 years 11 months ago
2000
IEEE
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
SSTA has received a considerable amount of attention in recent years. However, it is a general rule that any approach can only be as accurate as the underlying models. Thus, varia...
VTS
2000
IEEE
13 years 11 months ago
2000
IEEE
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the dela...