306 search results - page 15 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
The synchronous computational model with its simple computation and communication mechanism makes it easy to describe, simulate and formally verify synchronous embedded systems at...
ISLPED
1999
ACM
13 years 11 months ago
1999
ACM
Abstract – In this paper, we propose a modeling approach for the average power consumption of macro-blocks that are typically used in digital signal processing (DSP) systems, suc...
TMC
2012
11 years 9 months ago
2012
—Characterizing the performance of ad hoc networks is one of the most intricate open challenges; conventional ideas based on information-theoretic techniques and inequalities hav...
ISQED
2003
IEEE
14 years 19 days ago
2003
IEEE
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
IISWC
2008
IEEE
14 years 1 months ago
2008
IEEE
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...