306 search results - page 7 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
ICCAD
2002
IEEE
14 years 8 days ago
2002
IEEE
The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is exp...
ENTCS
2010
13 years 7 months ago
2010
This paper extends previous work on the compilation of higher-order imperative languages into digital circuits [4]. We introduce concurrency, an essential feature in the context o...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
: Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes are adopted to reduce...
DELTA
2006
IEEE
13 years 11 months ago
2006
IEEE
The difficulties of designing nanoscale circuits include the need for regular circuit structure and controlling the timing requirements. A cellular array has highly regular struct...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...