306 search results - page 8 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
TVLSI
2002
13 years 7 months ago
2002
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...
JELIA
2004
Springer
14 years 21 days ago
2004
Springer
Statistical default logic is a variation of classical (i.e., Reiter’s) default logic designed to represent basic inference forms common in inferential statistics. In this paper ...