306 search results - page 9 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
TCAD
2008
13 years 7 months ago
2008
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
DAC
2006
ACM
13 years 11 months ago
2006
ACM
Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and e...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their ”expected delay” over input data space. This paradigm shift calls for ...
GLVLSI
2003
IEEE
14 years 19 days ago
2003
IEEE
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
Electrical Modeling for High Bandwidth IO Link Chirayu Amin, Chandramouli Kashyap ¬ Intel Corp., Hillsboro, OR Prateek Bhansali ¬ Univ. of Minnesota, Mi...