Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these ...
Partially depleted silicon-on-insulator (PD-SOI) has emerged as a technology of choice for high-performance low-power deep-submicrometer digital integrated circuits. An important c...
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
Jonathan A. Clarke, George A. Constantinides, Pete...
— Low-power consumption has become a highly important concern for synchronous standard-cell design, and consequently mandates the use of low-power design methodologies and techni...
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will...