61 search results - page 7 / 13 » Statistical Leakage and Timing Optimization for Submicron Pr... |
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
We propose a novel design flow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is de...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— The impact of process variations increases as technology scales to nanometer region. Under large process variations, the path and arc/node criticality [18] provide effe...