1459 search results - page 23 / 292 » Statistical Modeling for Circuit Simulation |
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between per...
ITC
1999
IEEE
13 years 12 months ago
1999
IEEE
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...
DATE
2002
IEEE
14 years 17 days ago
2002
IEEE
Due to the increasing operating frequencies and the manner in which the corresponding integrated circuits and systems must be designed, the extraction, modeling and simulation of ...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simu...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
In this paper, we analyze the effect of jitter in track and hold circuits. The output spectrum is obtained in terms of the system function of the track and hold. It is a fairly g...