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ICCAD
2000
IEEE
88views Hardware» more  ICCAD 2000»
14 years 2 months ago
Hierarchical Interconnect Circuit Models
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...
DATE
2002
IEEE
126views Hardware» more  DATE 2002»
14 years 3 months ago
Automated Modeling of Custom Digital Circuits for Test
Models meant for logic verification and simulation are often used for ATPG. For custom digital circuits, these models contain many tristate devices, which leads to lower fault co...
Soumitra Bose
ASPDAC
2006
ACM
88views Hardware» more  ASPDAC 2006»
14 years 4 months ago
Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation
— A substrate-coupling equivalent circuit can be derived for an arbitrary guard ring test structure by way of F-matrix computation. The derived netlist represents a unified impe...
Daisuke Kosaka, Makoto Nagata
ISCAS
2006
IEEE
86views Hardware» more  ISCAS 2006»
14 years 4 months ago
Fast timing analysis of plane circuits via two-layer CNN-based modeling
Abstract— A fast timing analysis of plane circuits via two-layer CNNbased modeling, which is necessary for the solution of power/signal integrity problems in printed circuit boar...
Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifum...
CHES
2005
Springer
117views Cryptology» more  CHES 2005»
14 years 3 months ago
DPA Leakage Models for CMOS Logic Circuits
In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate...
Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa