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» Statistical Power Estimation for FPGA
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ASPDAC
2004
ACM
107views Hardware» more  ASPDAC 2004»
14 years 24 days ago
Interconnect capacitance estimation for FPGAs
Abstract—The dynamic power consumed by a digital CMOS circuit is directly proportional to capacitance. In this paper, we consider pre-routing capacitance estimation for FPGAs and...
Jason Helge Anderson, Farid N. Najm
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 7 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
FPL
2004
Springer
93views Hardware» more  FPL 2004»
14 years 23 days ago
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays
This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPG...
Steven J. E. Wilton, Su-Shin Ang, Wayne Luk
CHES
2005
Springer
123views Cryptology» more  CHES 2005»
14 years 28 days ago
Improved Higher-Order Side-Channel Attacks with FPGA Experiments
We demonstrate that masking a block cipher implementation does not sufficiently improve its security against side-channel attacks. Under exactly the same hypotheses as in a Differ...
Eric Peeters, François-Xavier Standaert, Ni...
FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
14 years 1 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk