246 search results - page 20 / 50 » Statistical gate sizing for timing yield optimization |
MICRO
2007
IEEE
14 years 3 months ago
2007
IEEE
Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in fu...
SAC
2002
ACM
13 years 8 months ago
2002
ACM
We investigate the universal characteristics of the simulated time horizon of the basic conservative parallel algorithm when implemented on regular lattices. This technique [1, 2]...
TVLSI
2002
13 years 8 months ago
2002
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
MICCAI
2005
Springer
14 years 9 months ago
2005
Springer
Deforming a digital atlas towards a patient image allows the simultaneous segmentation of several structures. Such an intersubject registration is difficult as the deformations to ...
ICCAD
1997
IEEE
14 years 1 months ago
1997
IEEE
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...