Sciweavers

70 search results - page 8 / 14
» Step-wise Refinement Design Example Using LOTOS
Sort
View
CODES
1998
IEEE
13 years 12 months ago
Software timing analysis using HW/SW cosimulation and instruction set simulator
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculate...
Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-V...
DATE
2004
IEEE
152views Hardware» more  DATE 2004»
13 years 11 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana
LAWEB
2009
IEEE
14 years 2 months ago
Promoting Creative Design through Toolkits
—Computer science academics and professionals typically consider their contributions in terms of the algorithms, applications, and techniques that they develop. Yet equally impor...
Saul Greenberg
COMPSAC
2002
IEEE
14 years 17 days ago
Framework for Goal Driven System Design
Architecture has been identified as a main tool for high quality system development. It encapsulates the earliest design decisions of the system under development. These decisions...
Juha Savolainen, Juha Kuusela
ENTCS
2006
112views more  ENTCS 2006»
13 years 7 months ago
Interface Automata with Complex Actions
Many formalisms use interleaving to model concurrency. To describe some system behaviours appropriately, we need to limit interleaving. For example, in componentbased systems, we ...
Shahram Esmaeilsabzali, Farhad Mavaddat, Nancy A. ...