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» Storage coding for wear leveling in flash memories
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ISLPED
1995
ACM
112views Hardware» more  ISLPED 1995»
13 years 11 months ago
Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors
Analog techniques can lead to ultra-efficient computational systems when applied to the right applications. The problem of associative memory is well suited to array-based analog ...
Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. ...
BTW
2009
Springer
146views Database» more  BTW 2009»
14 years 2 months ago
Towards Flash Disk Use in Databases - Keeping Performance While Saving Energy?
Abstract: Green computing or energy saving when processing information is primarily considered a task of processor development. We, however, advocate that a holistic approach is ne...
Theo Härder, Karsten Schmidt 0002, Yi Ou, Seb...
TIT
2010
90views Education» more  TIT 2010»
13 years 2 months ago
Correcting limited-magnitude errors in the rank-modulation scheme
We study error-correcting codes for permutations under the infinity norm, motivated the rank-modulation scheme for flash memories. In this scheme, a set of n flash cells are combin...
Itzhak Tamo, Moshe Schwartz
TIT
2010
111views Education» more  TIT 2010»
13 years 2 months ago
Designing floating codes for expected performance
Floating codes are codes designed to store multiple values in a Write Asymmetric Memory, with applications to flash memory. In this model, a memory consists of a block of n cells, ...
Flavio Chierichetti, Hilary Finucane, Zhenming Liu...
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
13 years 11 months ago
Use ECP, not ECC, for hard failures in resistive memories
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
Stuart E. Schechter, Gabriel H. Loh, Karin Straus,...