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» Stream Programming on General-Purpose Processors
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ISLPED
1999
ACM
150views Hardware» more  ISLPED 1999»
13 years 12 months ago
Using dynamic cache management techniques to reduce energy in a high-performance processor
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. P...
CCS
2008
ACM
13 years 9 months ago
When good instructions go bad: generalizing return-oriented programming to RISC
This paper reconsiders the threat posed by Shacham's "return-oriented programming" -- a technique by which WX-style hardware protections are evaded via carefully cr...
Erik Buchanan, Ryan Roemer, Hovav Shacham, Stefan ...
MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
13 years 12 months ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...
ISSS
1995
IEEE
100views Hardware» more  ISSS 1995»
13 years 11 months ago
Power analysis and low-power scheduling techniques for embedded DSP software
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...
Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, M...
CASES
2007
ACM
13 years 11 months ago
Hierarchical coarse-grained stream compilation for software defined radio
Software Defined Radio (SDR) is an emerging embedded domain where the physical layer of wireless protocols is implemented in software rather than the traditional application speci...
Yuan Lin, Manjunath Kudlur, Scott A. Mahlke, Trevo...