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ISQED
2005
IEEE
120views Hardware» more  ISQED 2005»
14 years 3 months ago
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
This paper presents a novel compact passive modeling technique for high-performance RF passives and interconnects modeled as high-order RLCM circuits. The new method is based on a...
Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan
CP
2005
Springer
14 years 3 months ago
Domain Reduction for the Circuit Constraint
Abstract. We present an incomplete filtering algorithm for the circuit constraint. The filter removes redundant values by eliminating nonHamiltonian edges from the associated gra...
Latife Genç Kaya, John N. Hooker
VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
14 years 10 months ago
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos
DAC
2005
ACM
13 years 11 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes