871 search results - page 14 / 175 » Streaming Reduction Circuit |
ICCAD
2005
IEEE
14 years 6 months ago
2005
IEEE
— In this paper we present a parameterized reduction technique for non-linear systems. Our approach combines an existing non-parameterized trajectory piecewise linear method for ...
DAC
2003
ACM
14 years 3 months ago
2003
ACM
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
EURODAC
1995
IEEE
14 years 1 months ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
ISQED
2005
IEEE
14 years 3 months ago
2005
IEEE
Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primar...
DAC
1995
ACM
14 years 1 months ago
1995
ACM
Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...