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SPAA
2004
ACM
14 years 3 months ago
The potential in energy efficiency of a speculative chip-multiprocessor
While lower supply voltage is effective for energy reduction, it suffers performance loss. To mitigate the loss, we propose to execute only the part, which does not have any influ...
Yuu Tanaka, Toshinori Sato, Takenori Koushiro
DAC
2003
ACM
14 years 10 months ago
Power grid reduction based on algebraic multigrid principles
With the scaling of technology, power grid noise is becoming increasingly significant for circuit performance. A typical power grid circuit contains millions of linear elements, m...
Haihua Su, Emrah Acar, Sani R. Nassif
DAC
2004
ACM
14 years 10 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
14 years 2 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
DAC
1996
ACM
14 years 2 months ago
Glitch Analysis and Reduction in Register Transfer Level
: We presentdesign-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the contro...
Anand Raghunathan, Sujit Dey, Niraj K. Jha