871 search results - page 37 / 175 » Streaming Reduction Circuit |
ISI
2008
Springer
13 years 10 months ago
2008
Springer
In this paper, we study the problem of anomaly detection in high-dimensional network streams. We have developed a new technique, called Stream Projected Ouliter deTector (SPOT), t...
CSREAESA
2004
13 years 11 months ago
2004
: In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal opt...
ICCAD
1999
IEEE
14 years 2 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
CODES
2008
IEEE
14 years 4 months ago
2008
IEEE
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit ...