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CODES
2008
IEEE
13 years 11 months ago
Power reduction via macroblock prioritization for power aware H.264 video applications
As the importance of multimedia applications in hand-held devices increases, the computational strain and corresponding demand for energy in such devices continues to grow. Portab...
Michael A. Baker, Viswesh Parameswaran, Karam S. C...
DAC
1999
ACM
14 years 2 months ago
Interconnect Analysis: From 3-D Structures to Circuit Models
In this survey paper we describethe combination of: discretized integral formulations, sparsication techniques, and krylov-subspace based model-order reduction that has led to rob...
Mattan Kamon, Nuno Alexandre Marques, Yehia Massou...
ASPDAC
1999
ACM
60views Hardware» more  ASPDAC 1999»
14 years 2 months ago
Timing Optimization of Logic Network Using Gate Duplication
We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication...
Chun-hong Chen, Chi-Ying Tsui
DATE
2007
IEEE
154views Hardware» more  DATE 2007»
14 years 4 months ago
Soft error rate analysis for sequential circuits
Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensiv...
Natasa Miskov-Zivanov, Diana Marculescu
CORR
2010
Springer
104views Education» more  CORR 2010»
13 years 10 months ago
Heuristic approach to optimize the number of test cases for simple circuits
In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circ...
S. M. Thamarai, K. Kuppusamy, T. Meyyappan