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ICCD
2002
IEEE
160views Hardware» more  ICCD 2002»
14 years 6 months ago
Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams
We represent switching activity in VLSI circuits using a graphical probabilistic model based on Cascaded Bayesian Networks (CBN’s). We develop an elegant method for maintaining ...
Sanjukta Bhanja, N. Ranganathan
VLSID
2002
IEEE
107views VLSI» more  VLSID 2002»
14 years 10 months ago
Estimation of Maximum Power-Up Current
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...
Fei Li, Lei He, Kewal K. Saluja
ISQED
2006
IEEE
132views Hardware» more  ISQED 2006»
14 years 4 months ago
Leakage Biased Sleep Switch Domino Logic
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...
Zhiyu Liu, Volkan Kursun
COCO
2008
Springer
88views Algorithms» more  COCO 2008»
13 years 11 months ago
Approximation of Natural W[P]-Complete Minimisation Problems Is Hard
We prove that the weighted monotone circuit satisfiability problem has no fixed-parameter tractable approximation algorithm with constant or polylogarithmic approximation ratio un...
Kord Eickmeyer, Martin Grohe, Magdalena Grübe...
MEMOCODE
2010
IEEE
13 years 7 months ago
FPGA-based combined architecture for stream categorization and intrusion detection
This paper presents a working solution for the MEMOCODE 2010 design contest. The design presented in this paper is implemented in the Xilinx V5LX330 FPGA as a custom circuit. The s...
Sunil Shukla, Rodric Rabbah, Martin Vorbach