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ASPDAC
2009
ACM
164views Hardware» more  ASPDAC 2009»
14 years 1 months ago
High-performance global routing with fast overflow reduction
Global routing is an important step for physical design. In this paper, we develop a new global router, NTUgr, that contains three major steps: prerouting, initial routing, and enh...
Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang
TCSV
2002
66views more  TCSV 2002»
13 years 9 months ago
Multiframe blocking-artifact reduction for transform-coded video
A major drawback of block-based still-image or video-compression methods at low rates is the visible block boundaries that are also known as blocking artifacts. Several methods hav...
Bahadir K. Gunturk, Yucel Altunbasak, Russell M. M...
FCCM
2008
IEEE
112views VLSI» more  FCCM 2008»
14 years 4 months ago
Power-Aware and Branch-Aware Word-Length Optimization
Power reduction is becoming more important as circuit size increases. This paper presents a tool called PowerCutter which employs accuracy-guaranteed word-length optimization to r...
William G. Osborne, José Gabriel F. Coutinh...
DATE
2007
IEEE
126views Hardware» more  DATE 2007»
14 years 4 months ago
WAVSTAN: waveform based variational static timing analysis
— We present a waveform based variational static timing analysis methodology. It is a timing paradigm that lies midway between convention static delay approximations and full dyn...
Saurabh K. Tiwary, Joel R. Phillips
GLVLSI
2007
IEEE
115views VLSI» more  GLVLSI 2007»
14 years 4 months ago
Novel architectures for efficient (m, n) parallel counters
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
Sreehari Veeramachaneni, Lingamneni Avinash, Kirth...