871 search results - page 97 / 175 » Streaming Reduction Circuit |
VTS
2003
IEEE
14 years 3 months ago
2003
IEEE
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
ISLPED
2003
ACM
14 years 3 months ago
2003
ACM
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
ISLPED
1997
ACM
14 years 1 months ago
1997
ACM
Significand pre-alignment is a pre requisite for floating point additions. This paper1 addresses the architectural design and energy delay evaluation of a Low Power Barrel Switch ...
ICCAD
2010
IEEE
13 years 8 months ago
2010
IEEE
For a variety of signal processing applications polynomials are implemented in circuits. Recent work on polynomial datapath optimization achieved significant reductions of hardware...
IJCAI
1989
13 years 11 months ago
1989
A real-time AI system in the real world needs to monitor an immense volume of data. To do this, the system must filter out much of the incoming data. However, it must remain re ...