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DATE
2010
IEEE
156views Hardware» more  DATE 2010»
14 years 1 months ago
Domain specific architecture for next generation wireless communication
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo,...
STTT
2010
115views more  STTT 2010»
13 years 7 months ago
Scalable shared memory LTL model checking
Recent development in computer hardware has brought more wide-spread emergence of shared memory, multi-core systems. These architectures offer opportunities to speed up various ta...
Jiri Barnat, Lubos Brim, Petr Rockai
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
13 years 7 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
CCGRID
2002
IEEE
14 years 1 months ago
Symphony - A Java-Based Composition and Manipulation Framework for Computational Grids
We introduce the Symphony framework, a software ion layer that can sit on top of grid systems. Symphony provides a unified API for grid application developers and offers a graphic...
Markus Lorch, Dennis G. Kafura
MICRO
2010
IEEE
172views Hardware» more  MICRO 2010»
13 years 6 months ago
Architectural Support for Fair Reader-Writer Locking
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
Enrique Vallejo, Ramón Beivide, Adriá...