Sciweavers

114 search results - page 21 / 23
» Sub-threshold design: the challenges of minimizing circuit e...
Sort
View
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
14 years 2 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
ICCAD
2007
IEEE
144views Hardware» more  ICCAD 2007»
14 years 4 months ago
Voltage island-driven floorplanning
— Energy efficiency has become one of the most important issues to be addressed in today’s System-on-a-Chip (SoC) designs. One way to lower the power consumption is to reduce ...
Qiang Ma, Evangeline F. Y. Young
CASES
2004
ACM
14 years 29 days ago
A post-compiler approach to scratchpad mapping of code
ScratchPad Memories (SPMs) are commonly used in embedded systems because they are more energy-efficient than caches and enable tighter application control on the memory hierarchy...
Federico Angiolini, Francesco Menichelli, Alberto ...
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
14 years 24 days ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
ADHOC
2007
122views more  ADHOC 2007»
13 years 7 months ago
Minimum latency joint scheduling and routing in wireless sensor networks
Wireless sensor networks are expected to be used in a wide range of applications from environment monitoring to event detection. The key challenge is to provide energy efficient ...
Gang Lu, Bhaskar Krishnamachari