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VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
14 years 10 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
ICSE
2004
IEEE-ACM
14 years 10 months ago
Design of Large-Scale Polylingual Systems
Abstract. Building systems from existing applications written in two or more languages is common practice. Such systems are polylingual. Polylingual systems are relatively easy to ...
Mark Grechanik, Don S. Batory, Dewayne E. Perry
VMCAI
2010
Springer
14 years 7 months ago
Improved Model Checking of Hierarchical Systems
We present a unified game-based approach for branching-time model checking of hierarchical systems. Such systems are exponentially more succinct than standard state-transition gra...
Benjamin Aminof, Orna Kupferman, Aniello Murano
EUROSYS
2007
ACM
14 years 7 months ago
STMBench7: a benchmark for software transactional memory
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...
Rachid Guerraoui, Michal Kapalka, Jan Vitek
ICCAD
2004
IEEE
94views Hardware» more  ICCAD 2004»
14 years 6 months ago
Timing macro-modeling of IP blocks with crosstalk
With the increase of design complexities and the decrease of minimal feature sizes, IP reuse is becoming a common practice while crosstalk is becoming a critical issue that must b...
Ruiming Chen, Hai Zhou