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» Synchronous Elastic Circuits
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ASYNC
2007
IEEE
132views Hardware» more  ASYNC 2007»
14 years 2 months ago
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
ICCD
2007
IEEE
206views Hardware» more  ICCD 2007»
14 years 5 months ago
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
Julian J. H. Pontes, Rafael Soares, Ewerson Carval...
DFT
2006
IEEE
122views VLSI» more  DFT 2006»
14 years 8 days ago
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpi...
ASPDAC
2001
ACM
127views Hardware» more  ASPDAC 2001»
14 years 7 days ago
High-level design for asynchronous logic
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
Ross Smith, Michiel M. Ligthart
ICCAD
2001
IEEE
163views Hardware» more  ICCAD 2001»
14 years 5 months ago
Predicting the Performance of Synchronous Discrete Event Simulation Systems
In this paper we propose a model to predict the performance of synchronous discrete event simulation. The model considers parameters including the number of active objects per cyc...
Jinsheng Xu, Moon-Jung Chung