95 search results - page 4 / 19 » Synchronous Interlocked Pipelines |
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modula...
MEMOCODE
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents results on processor specification from a specialized high-level finite state machine (FSM) language. The language is an extension and enhancement of earlier...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
— This paper presents a method for correct-by-construction microarchitectural pipelining that handles cyclic systems with dependencies between iterations. Our method combines pre...