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PPOPP
2010
ACM
14 years 7 months ago
Scalable communication protocols for dynamic sparse data exchange
Many large-scale parallel programs follow a bulk synchronous parallel (BSP) structure with distinct computation and communication phases. Although the communication phase in such ...
Torsten Hoefler, Christian Siebert, Andrew Lumsdai...
ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 6 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
RTSS
2008
IEEE
14 years 4 months ago
Predictable Interrupt Management and Scheduling in the Composite Component-Based System
This paper presents the design of user-level scheduling hierarchies in the Composite component-based system. The motivation for this is centered around the design of a system that...
Gabriel Parmer, Richard West
ICCD
2006
IEEE
97views Hardware» more  ICCD 2006»
14 years 6 months ago
Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Sa...
PPOPP
1990
ACM
14 years 1 months ago
Concurrent Aggregates (CA)
Toprogrammassivelyconcurrent MIMDmachines, programmersneed tools for managingcomplexity. One important tool that has been used in the sequential programmingworld is hierarchies of...
Andrew A. Chien, William J. Dally