47 search results - page 5 / 10 » Synchronous Transfer Architecture (STA) |
ISPA
2007
Springer
14 years 1 months ago
2007
Springer
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
IICS
2003
Springer
14 years 24 days ago
2003
Springer
Middleware technologies have been facilitating the communication between the distributed applications. Traditional messaging system’s are synchronous and have inherent weaknesses...
ICCAD
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
ICS
1999
Tsinghua U.
13 years 12 months ago
1999
Tsinghua U.
The Virtual Interface (VI) Architecture provides protected userlevel communication with high delivered bandwidth and low permessage latency, particularly for small messages. The V...
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...