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ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
14 years 2 months ago
Technology Mapping for Reliability Enhancement in Logic Synthesis
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
Zhaojun Wo, Israel Koren
FDL
2005
IEEE
14 years 2 months ago
Hardware Synthesis of Parallel Machines from SystemC
Heterogeneous system specifications implicitly assume parallel execution of their components that rely on supporting platform architectures and operating systems. Unfortunately, c...
Antoni Portero, Lluis Ribas, Jordi Carrabina
SCESM
2006
ACM
238views Algorithms» more  SCESM 2006»
14 years 2 months ago
Nobody's perfect: interactive synthesis from parametrized real-time scenarios
As technical systems keep growing more complex and sophisticated, designing software for the safety-critical coordination between their components becomes increasingly difficult....
Holger Giese, Stefan Henkler, Martin Hirsch, Flori...
SAM
2004
98views Hardware» more  SAM 2004»
13 years 10 months ago
Scenario Synthesis from Imprecise Requirements
Discovering faults in requirements specifications for distributed reactive systems is a challenging problem since many issues that need to be uncovered are a result of subtle compo...
Bill Mitchell, Robert Thomson, Paul Bristow
LCTRTS
2007
Springer
14 years 3 months ago
Interface synthesis for heterogeneous multi-core systems from transaction level models
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...
Hansu Cho, Samar Abdi, Daniel Gajski