115 search results - page 18 / 23 » Synthesis of Asynchronous Hardware from Petri Nets |
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
ACSD
2005
IEEE
14 years 1 months ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
DAC
1998
ACM
14 years 8 months ago
1998
ACM
We present a Petri net theoretic approach to the software synthesis problem that can synthesize ordinary C programs from processbased concurrent specifications without the need for...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
TCAD
1998
13 years 7 months ago
1998
Most existing tools for the synthesisof asynchronouscircuits from Signal Transition Graphs (STGs) derive the reachability graph for the calculation of logic equations. This paper ...