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» Synthesis of Asynchronous Hardware from Petri Nets
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DATE
2000
IEEE
88views Hardware» more  DATE 2000»
13 years 12 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
ICCAD
1996
IEEE
127views Hardware» more  ICCAD 1996»
13 years 11 months ago
Comparing models of computation
We give a denotational framework (a "meta model") within which certain properties of models of computation can be understood and compared. It describes concurrent proces...
Edward A. Lee, Alberto L. Sangiovanni-Vincentelli
CPE
1994
Springer
170views Hardware» more  CPE 1994»
13 years 11 months ago
Automatic Scalability Analysis of Parallel Programs Based on Modeling Techniques
When implementingparallel programs forparallel computer systems the performancescalability of these programs should be tested and analyzed on different computer configurations and...
Allen D. Malony, Vassilis Mertsiotakis, Andreas Qu...
SIGMETRICS
2002
ACM
107views Hardware» more  SIGMETRICS 2002»
13 years 7 months ago
Passage time distributions in large Markov chains
Probability distributions of response times are important in the design and analysis of transaction processing systems and computercommunication systems. We present a general tech...
Peter G. Harrison, William J. Knottenbelt
ISPD
2000
ACM
97views Hardware» more  ISPD 2000»
13 years 12 months ago
Routability-driven repeater block planning for interconnect-centric floorplanning
In this paper we present a repeater block planning algorithm for interconnect-centric floorplanning. We introduce the concept of independent feasible regions for repeaters and der...
Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh