This paper presents algorithms that (1) facilitate systemindependent synthesis of timing-interfaces for subsystems and (2) system-level selection of interfaces to minimize CPU loa...
Insik Shin, Moris Behnam, Thomas Nolte, Mikael Nol...
This paper presents a new approach to hierarchical high-level synthesis with respect to internal register-transfer structures of complex components. Entire subdesigns can efficie...
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified sy...
We present an approach to the analysis and optimization of heterogeneous distributed embedded systems for hard real-time applications. The systems are heterogeneous not only in te...