663 search results - page 85 / 133 » Synthesis of Self-Testable Controllers |
114
Voted
ASAP
2007
IEEE
15 years 4 months ago
2007
IEEE
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
127
Voted
ICCAD
2006
IEEE
15 years 11 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
173
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ECBS
1996
IEEE
15 years 6 months ago
1996
IEEE
In this paper, it is shown that, through the use of Model-Integrated Program Synthesis MIPS, parallel real-time implementations of image processing data ows can be synthesized fro...
152
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ISSS
1995
IEEE
15 years 6 months ago
1995
IEEE
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
124
Voted
DAC
2008
ACM
16 years 3 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...