70 search results - page 8 / 14 » Synthesis of Speed Independent Circuits Based on Decompositi... |
ISPD
2006
ACM
14 years 1 months ago
2006
ACM
In this paper, we propose more accurate power/ground network circuit model, which consider both via and ground bounce effects to improve the performance estimation accuracy of on-...
ITC
1999
IEEE
13 years 12 months ago
1999
IEEE
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
EURODAC
1990
IEEE
13 years 11 months ago
1990
IEEE
In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational circuits. The ...
CIIA
2009
13 years 8 months ago
2009
In this paper, we present a new synthesis feature namely, "Xor matching", and the foldback product term synthesis for Complex Programmable Logic Devices (CPLD) architectu...
DATE
2000
IEEE
14 years 23 hour ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...