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» Synthesis of networks on chips for 3D systems on chips
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ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
14 years 3 months ago
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
Henrique C. Freitas, Dalton M. Colombo, Fernanda L...
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 8 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
14 years 2 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
HIPC
2005
Springer
14 years 2 months ago
The Potential of On-Chip Multiprocessing for QCD Machines
We explore the opportunities offered by current and forthcoming VLSI technologies to on-chip multiprocessing for Quantum Chromo Dynamics (QCD), a computational grand challenge for ...
Gianfranco Bilardi, Andrea Pietracaprina, Geppino ...
DATE
2008
IEEE
100views Hardware» more  DATE 2008»
14 years 3 months ago
User-Aware Dynamic Task Allocation in Networks-on-Chip
In this paper, we propose a run-time strategy for allocating the application tasks to platform resources in homogeneous Networks-on-Chip (NoCs). As novel contribution, we incorpor...
Chen-Ling Chou, Radu Marculescu