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» Synthesis of networks on chips for 3D systems on chips
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DSD
2010
IEEE
99views Hardware» more  DSD 2010»
13 years 8 months ago
Trading Hardware Overhead for Communication Performance in Mesh-Type Topologies
—Several alternatives of mesh-type topologies have been published for the use in Networks-on-Chip. Due to their regularity, mesh-type topologies often serve as a foundation to in...
Claas Cornelius, Philipp Gorski, Stephan Kubisch, ...
HPCA
2007
IEEE
14 years 9 months ago
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications
Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of powe...
Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlk...
MOBISYS
2005
ACM
14 years 8 months ago
LiveMail: personalized avatars for mobile entertainment
LiveMail is a prototype system that allows mobile subscribers to communicate using personalized 3D face models created from images taken by their phone cameras. The user takes a s...
Miran Mosmondor, Tomislav Kosutic, Igor S. Pandzic
CAV
2009
Springer
156views Hardware» more  CAV 2009»
14 years 3 months ago
Towards Performance Prediction of Compositional Models in Industrial GALS Designs
Systems and Networks on Chips (NoCs) are a prime design focus of many hardware manufacturers. In addition to functional verification, which is a difficult necessity, the chip desi...
Nicolas Coste, Holger Hermanns, Etienne Lantreibec...
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
14 years 3 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...