Sciweavers

419 search results - page 49 / 84
» Synthesis of networks on chips for 3D systems on chips
Sort
View
VLSID
1998
IEEE
116views VLSI» more  VLSID 1998»
14 years 27 days ago
Synthesis of Testable RTL Designs
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
C. P. Ravikumar, Sumit Gupta, Akshay Jajoo
DAC
2008
ACM
14 years 9 months ago
An 8x8 run-time reconfigurable FPGA embedded in a SoC
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. ...
Sumanta Chaudhuri, Sylvain Guilley, Florent Flamen...
VLSID
2010
IEEE
155views VLSI» more  VLSID 2010»
14 years 16 days ago
Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore
Abstract—Microfluidics-based biochips are revolutionizing highthroughput sequencing, parallel immunoassays, clinical diagnostics, and drug discovery. These devices enable the pre...
Krishnendu Chakrabarty
ISCA
2011
IEEE
324views Hardware» more  ISCA 2011»
13 years 11 days ago
Prefetch-aware shared resource management for multi-core systems
Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these share...
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N....
ICC
2007
IEEE
127views Communications» more  ICC 2007»
14 years 3 months ago
A Memory Unit for Priority Management in IPSec Accelerators
— This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at d...
Luigi Dadda, Alberto Ferrante, Marco Macchetti