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» Synthesis of networks on chips for 3D systems on chips
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SBCCI
2004
ACM
117views VLSI» more  SBCCI 2004»
14 years 2 months ago
Reducing test time with processor reuse in network-on-chip based systems
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
Alexandre M. Amory, Érika F. Cota, Marcelo ...
CASES
2006
ACM
14 years 2 months ago
A network agent for diagnosis and analysis of real-time Ethernet networks
Within the field of automation technology the use of Industrial Ethernet is rising. This in turn demands devices capable of precisely recording, analyzing, and manipulating commu...
Hans-Peter Löb, Rainer Buchty, Wolfgang Karl
AHS
2006
IEEE
145views Hardware» more  AHS 2006»
14 years 11 days ago
The Gannet Service-Based SoC: A Service-level Reconfigurable Architecture
We propose a novel type of dynamically reconfigurable System-on-Chip architecture, the Gannet service-based architecture. This novel concept addresses the issue of systemlevel rec...
Wim Vanderbauwhede
DSN
2008
IEEE
13 years 10 months ago
An accurate flip-flop selection technique for reducing logic SER
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In...
Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
14 years 2 months ago
A High Throughput String Matching Architecture for Intrusion Detection and Prevention
Network Intrusion Detection and Prevention Systems have emerged as one of the most effective ways of providing security to those connected to the network, and at the heart of alm...
Lin Tan, Timothy Sherwood