419 search results - page 78 / 84 » Synthesis of networks on chips for 3D systems on chips |
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
VLSID
2004
IEEE
14 years 9 months ago
2004
IEEE
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract. Congestion has negative effects on network performance. In this paper, a novel congestion control strategy is presented for Networks-on-Chip (NoC). For this purpose we in...
MICRO
2006
IEEE
14 years 2 months ago
2006
IEEE
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched...
INFOCOM
2005
IEEE
14 years 2 months ago
2005
IEEE
Packet Classification (PC) has been a critical data path function for many emerging networking applications. An interesting approach is the use of TCAM to achieve deterministic, hi...